We are a provider of differentiated and complex Analog, Mixed-Signal & RF Silicon IP cores. We constantly strive to create and provide IP cores that are best-in-class and thereby make our customers’ solutions differentiated and low-cost.
Digital Designers - Bangalore
10/13/2016 2:35:27 AM
Exposure to advanced technology nodes (40nm, 28nm) and their associated issues is desirable .
Knowledge in high-speed SERDES PHY or Controller design is desirable.
The candidate should possess strong engineering fundamentals, logic in particular. Should have a grasp of the basics of timing and should have a working knowledge of Verilog. System Verilog knowledge is a plus. Ability to work independently and coordinate with a team is a must. Knowledge of a scripting language (Python/Perl/Tcl) is a plus.
Working experience: 3-5 years is desirable, though if the candidate is good, we will make exceptions