Description

You will perform Analog Mixed-Signal (AMS) verification for IP and subsystem-level designs using SystemVerilog, Wreal, and Verilog-AMS.

Responsibilities

• Develop and maintain mixed-signal testbenches and behavioral real-number models (RNM) for analog/digital interfaces.
• Drive functional and regression verification, ensuring coverage closure and model-to-SPICE correlation.
• Collaborate with analog and digital design teams to debug AMS integration and simulation issues.
• Utilize Cadence AMS Designer, Xcelium, Spectre, or Synopsys VCS AMS for simulation and verification flows.

Required Skills

• 5+ years of experience in AMS verification.
• Proficiency in SystemVerilog, Wreal, and Verilog-AMS.
• Hands-on experience with Synopsys VCS AMS, Cadence AMS Designer, or similar tools.
• Strong understanding of analog concepts including PLLs, ADC/DACs, SerDes, or Power Management IPs.
• Bachelor's degree in Engineering or related field.

Preferred Skills

• Scripting skills in Python, Perl, or TCL for automation and flow enhancements.

Key Skills

Education

Any Graduate