Description

Key Responsibilities:

• Testbench Development & Verification Execution: Design, build, and maintain functional verification environments at both block and full-chip SoC levels using SystemVerilog/UVM and Verilog-AMS/SystemVerilog RNM (Real Number Modeling).
• Verification Planning: Work closely with analog design, digital design, and architecture teams to review specs and author comprehensive verification plans and coverage metrics.
• Behavioral Modeling: Write and validate high-level analog behavioral models (Verilog-AMS, SystemVerilog, wreal) to enable fast, efficient full-chip mixed-signal co-simulations.
• Mixed-Signal Co-Simulation: Perform schematic/behavioral mixed-signal co-simulations using Cadence Virtuoso, Spectre, AMS Designer, or Synopsys XA/VCS tools.
• Coverage & Debugging: Write functional assertions (SVA), define coverage goals, analyze regression results, and debug differences between analog implementations and reference models.
• Automation & Scripting: Automate simulation flows, regression management, and report generation using Python, Perl, Tcl, or Shell scripts

Key Skills

Education

Bachelor's degree