Description

Own the functional verification of mixed-signal SoCs, building environments from block to full-chip level using SystemVerilog/UVM and Verilog-AMS.

This role is on-site.

Responsibilities

• Design and maintain verification environments at block and full-chip SoC levels using SystemVerilog/UVM and Verilog-AMS/SystemVerilog RNM.
• Develop behavioral models (Verilog-AMS, SystemVerilog, wreal) to enable efficient full-chip mixed-signal co-simulations.
• Execute schematic/behavioral mixed-signal co-simulations using Cadence Virtuoso, Spectre, AMS Designer, or Synopsys XA/VCS.
• Define coverage goals, write functional assertions (SVA), and debug discrepancies between analog implementations and reference models.
• Automate simulation flows, regression management, and reporting using Python, Perl, Tcl, or Shell scripts.

Required Skills

• 3+ years of experience in mixed-signal verification.
• Proficiency in SystemVerilog and UVM.
• Experience with Verilog-AMS and SystemVerilog RNM.
• Strong scripting skills in Python, Perl, Tcl, or Shell.
• Familiarity with Cadence Virtuoso, Spectre, AMS Designer, or Synopsys XA/VCS.
• Bachelor's degree in Electrical Engineering or related field.

Key Skills

Education

Bachelor's degree