Description

You will design and verify building blocks for Phase Locked Loops (PLLs) using FinFET technology.

Responsibilities

• Design PLL building blocks including VCO, charge-pump, dividers, state machines, LDO, bandgap, TDC, and interpolator circuits.
• Run pre-tape out verification flows to confirm design meets performance, power, reliability, and timing requirements.
• Collaborate with layout engineers to deliver physical designs.
• Define production and bench-level test plans for post-silicon characterization and silicon evaluation.

Required Skills

• Analog Circuit Design expertise in FinFET technology.
• Proficiency with Spectre, Hspice, and AFS simulation tools.
• Experience with Physical design and Static Timing Analysis (STA).
• Ability to use MATLAB, System Verilog, and Python for design and analysis.
• Knowledge of Tcl for methodology scripting.
• Experience managing design requirements for performance, power, and reliability.
• Strong analytical and problem-solving skills.

Preferred Skills

• Experience with FinFET and Dual Patterning nodes (16/14/10/7nm/5nm).
• Hands-on design of ADC, DAC, op-amps, and high-speed buffers.
• Knowledge of Digital PLL techniques, TDC, DSP, or control theory.
• Proficiency in Cadence ADE-L/ADE-XL and Calibre, ICV, or similar verification tools.

Key Skills

Education

Any Graduate