Description

Design and verify PLL building blocks for FinFET technology, owning the full cycle from schematic to post-silicon characterization.

This role is on-site.

Responsibilities

• Design PLL components including VCO, charge-pump, dividers, state machines, LDO, bandgap, TDC, and interpolators.
• Run pre-tapeout verification flows to ensure performance, power, reliability, and timing requirements.
• Collaborate with layout engineers to deliver physical designs.
• Define production and bench-level test plans for post-silicon characterization.

Required Skills

• 5+ years of experience in analog circuit design expertise in FinFET technology.
• Proficiency with Spectre, Hspice, and AFS simulation tools.
• Experience with physical design and Static Timing Analysis (STA).
• Ability to use MATLAB, System Verilog, and Python for design and analysis.
• Knowledge of Tcl for methodology scripting.
• Experience managing design requirements with strong analytical and problem-solving skills.

Preferred Skills

• Experience with FinFET and Dual Patterning nodes (16/14/10/7nm/5nm).
• Hands-on design of ADC, DAC, op-amps, and high-speed buffers.

Key Skills

Education

Any Graduate