Description

Drive ASIC design processes for advanced technology nodes, owning RTL coding, timing constraints, and lint checking.

This role is on-site.

Responsibilities

• Execute timing constraint development for 28nm, 16nm, and below nodes.
• Perform RTL coding and lint checking to ensure design integrity.
• Manage synthesis workflows using Genus or Fusion Compiler.
• Conduct timing analysis using PrimeTime.
• Utilize industry-standard CAD methodologies for design implementation.

Required Skills

• 10+ years of professional engineering experience.
• Proficiency with Synopsys PrimeTime.
• Experience with Cadence Genus or Synopsys Fusion Compiler/Design Compiler.
• Experience with advanced technology nodes including 28nm, 16nm, and below.
• Familiarity with CAD methodologies from Cadence, Synopsys, or Mentor.
• Proven track record in timing constraint development.
• Bachelor's degree in electronic engineering or equivalent qualification.

Preferred Skills

• Strong analytical, communication, and presentation skills.

Key Skills

Education

Bachelor's degree