Description

You own the end-to-end design of ASIC blocks within complex SoC programs.

Responsibilities

• Develop micro-architecture based on high-level specifications.
• Perform RTL design and coding using Verilog / SystemVerilog.
• Create efficient and reusable RTL logic.
• Conduct design reviews, debug issues, and resolve problems.
• Collaborate with verification, DFT, and physical design teams to meet targets.

Required Skills

• 6+ years of ASIC RTL design experience.
• Strong micro-architecture skills.
• Expert RTL coding in Verilog / SystemVerilog.
• Proven ability to create RTL logic independently.
• Solid background in ASIC design.
• Strong analytical and problem-solving capabilities.
• Ability to comprehend high-level design specifications.

Key Skills

Education

Not specified