Description

You will manage IP-level synthesis runs and ensure successful program execution within the IP team.

Responsibilities

• Define synthesis recipes in collaboration with block leads.
• Analyze results and debug failures alongside design leads.
• Act as a liaison between IP and SoC design teams regarding synthesis and physical layout issues.
• Sign off on IP quality for delivery into SoC.
• Work with Central Engineering teams on new flow adoption and execution.

Required Skills

• 5+ years of industry design experience.
• Proficiency with industry standard synthesis tools and flows including Design Compiler/FX.
• Experience with Formality, CDC, and Linting tools.
• Strong background in Verilog, System Verilog, and scripting.
• Proven experience in back-end timing closure.
• Strong analytical skills and attention to detail.
• Ability to independently drive tasks to completion and debug complex issues.
• Degree in any engineering or technical field.

Preferred Skills

• RTL design experience on large ASIC development projects.
• Knowledge of display technologies or IP integration within an SoC.

Key Skills

Education

Any Gradute