Description

You will own the end-to-end verification process for IP blocks and SoC components.

This role is on-site.

Responsibilities

• Build UVM test benches and own IP verification from inception to completion.
• Create coverage-driven verification plans based on design specifications.
• Execute, review, and refine plans to meet defined coverage targets.
• Set up regressions and triage failures to ensure stability.
• Debug and resolve design and verification issues through to closure.

Required Skills

• 5+ years of hands-on ASIC, IP, or SoC design verification experience.
• Experience building block-level UVM test benches, including drivers, scoreboards, sequences, constraints, and functional coverage models.
• Proficiency in scripting languages such as Python, Perl, or TCL.
• Strong understanding of architectural and micro-architectural design details.
• Experience with debugging complex design and verification issues.
• B.Tech or M.Tech in Microelectronics, Electrical Engineering, or Computer Science.

Preferred Skills

• Experience working on memory subsystems.

Key Skills

Education

Any Graduate