Description

You will focus on functional verification and debugging for high-performance IP development.

Responsibilities

• Develop and maintain directed and random verification tests for functional verification.
• Debug test failures to identify root causes and work with RTL and firmware engineers to resolve design defects.
• Execute functional and code coverage verification.
• Collaborate with architects, hardware engineers, and firmware engineers to define and verify new features.
• Provide technical support to cross-functional teams.

Required Skills

• 10+ years of ASIC design verification experience.
• Proficiency in Verilog and SystemVerilog.
• Hands-on experience with UVM verification libraries.
• Strong debugging skills in firmware and RTL code using simulation tools.
• Experience with C/C++.
• Background in DDR or Memory Controller verification.
• Any Graduate degree.

Preferred Skills

• Experience with PHY verification.
• Scripting proficiency in Python, Perl, or TCL.
• Understanding of Design for Test (DFT) methodologies and DFT verification.

Key Skills

Education

Any Gradute