Description

Key Skills: Place and Route, Physical Design, Fusion Compiler, Innovus, Python, TCL, Perl, UPF, STA, Power Gating

Good to Have Skills: Synthesis, Physical verification, AI/ML concepts, level-shifter design, voltage areas, power-state tables, electrical checks using FM & VSI, CAD automation mindset, debugging capabilities, multi-voltage design experience, advanced process nodes 3nm and 2nm technology.

Roles & Responsibilities:

• Develop Place and Route methodologies for various designs at advanced technology nodes including 3nm and 2nm.
• Work seamlessly with synthesis and signoff teams including STA, extraction, and Physical Verification to achieve best-in-class PPA.
• Drive power/performance/area convergence for SOCs implementation across multiple design projects.
• Script out utilities to automate different pieces of the implementation flow for improved efficiency.
• Support design teams at global sites through multiple PnR flow stages including chip finish flows.
• Interface with large design teams across the globe and own development for next generation synthesis flows.

Experience Required: 8-10 years of experience in CAD flow and methodology development on advanced nodes such as 3nm & 2nm. Hands-on experience in PNR flows including multi-voltage & power-gated designs. Strong problem-solving skills and analytical thinking required.

Education: Master's/Bachelor's Degree in Electronics Engineering with Minor in Computer Science preferred

Key Skills

Education

Any Graduate