Description

You will develop Place and Route methodologies for advanced technology nodes (3nm and 2nm) and drive power, performance, and area convergence for SOC implementations.

This role is on-site.

Responsibilities

• Develop PnR methodologies and support chip finish flows for multi-voltage, power-gated designs at 3nm and 2nm nodes.
• Collaborate with synthesis and signoff teams (STA, extraction, PV) to achieve optimal PPA.
• Automate implementation flows by scripting utilities in Python, TCL, or Perl to improve efficiency.
• Interface with global design teams to own development for next-generation synthesis flows.
• Debug complex design issues and support power gating and UPF implementation.

Required Skills

• 8+ years of experience in CAD flow and methodology development.
• Hands-on expertise with Fusion Compiler and Innovus.
• Strong background in Place and Route, Physical Design, and STA.
• Proficiency in scripting with Python, TCL, and Perl.
• Experience with UPF and Power Gating techniques.
• Understanding of multi-voltage design and advanced process nodes.

Preferred Skills

• Experience with Synthesis, Physical Verification, and electrical checks (FM & VSI).
• Familiarity with AI/ML concepts, level-shifter design, and voltage areas.
• Master's or Bachelor's Degree in Electronics Engineering with a minor in Computer Science.

Key Skills

Education

Any Graduate