Description

Design PLL building blocks and manage the full design cycle through silicon evaluation.

This role is on-site.

Responsibilities

• Design PLL building blocks including VCO, charge-pump, dividers, state machines, LDO, bandgap, TDC, and interpolator circuits.
• Execute pre-tapeout verification flows to validate performance, power, reliability, and timing requirements.
• Collaborate with layout engineers to deliver physical designs.
• Define production and bench-level test plans for post-silicon characterization and evaluation.

Required Skills

• Analog Circuit Design expertise in FinFET technology.
• Experience with PLL subblocks, feedback/compensation techniques, and high-speed buffers.
• Knowledge of Physical design, STA, and methodology scripting.
• Proficiency in simulation tools including Spectre, Hspice, and AFS.
• Hands-on experience with Verilog, Python, Perl, and Matlab.
• Ability to interpret DRC and LVS results using verification tools like Calibre or ICV.
• Strong analytical problem-solving skills and attention to detail.

Preferred Skills

• 3-5 years of semiconductor industry experience, specifically with FinFET and Dual Patterning nodes (16/14/10/7/5nm).
• Design experience with ADC, DAC, op-amps, and Fractional-N or spread-spectrum PLLs.

Key Skills

Education

Any Graduate