Description

You will design and develop CPU subsystems, IPs, and SoC integrations for next-generation processors.

Responsibilities

• Develop CPU subsystem front-end designs, focusing on microarchitecture and RTL.
• Deliver production-quality designs that meet specific Power, Performance, and Area (PPA) goals.
• Manage microarchitecture specification from high-level exploration through detailed design.
• Handle re-designing, porting, and updating existing designs to meet new technology advancements.
• Support functional verification teams by assisting with the execution of verification strategies.

Required Skills

• 6+ years of experience in ASIC design.
• Proficiency in RTL coding using Verilog and SystemVerilog.
• Hands-on experience with EDA tools, Lint, CDC, and timing analysis.
• Strong understanding of logic design principles, including power, performance, and timing implications.
• Experience with scripting languages such as Perl, Python, Shell, or TCL.
• Knowledge of clocking, reset architecture, and data flows.
• Familiarity with SoC bring-up, bus protocols, and register/address map verification.

Preferred Skills

• Experience with RISC-V, ARM, or x86 architectures and ISA.
• Knowledge of In-Order/Out-of-Order execution, cache coherency, and memory systems.
• Experience with Fetch Units, MMU/IO-MMU, Load-Store, and AMBA bus protocols.

Key Skills

Education

Any Graduate