Description

Lead design verification for IP, sub-systems, and SoC-level architectures.

This role is on-site.

Responsibilities

• Architect and implement design verification infrastructure from scratch.
• Develop and maintain UVM-based verification environments.
• Execute the full verification cycle for complex hardware designs.
• Verify ARM/RISC-V based CPU sub-systems or SoCs.
• Build verification tools and flows using scripting languages.

Required Skills

• 7+ years of hands-on experience with SystemVerilog and UVM methodology.
• 7+ years of experience in IP, sub-system, or SoC level verification.
• Proficiency in C or C++ based verification.
• Experience with AMBA, PCIe, DDR, USB, or Ethernet protocols.
• Strong scripting skills in Python, TCL, Perl, or Shell.
• Experience with EDA tools and verification flows.
• Proficiency with revision control systems such as Git, SVN, or Mercurial (Hg).

Preferred Skills

• Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience.

Key Skills

Education

Any Graduate