Description

You will own the micro-architecture and RTL development of design modules.

Responsibilities

• Micro-architect features to meet performance, power, and area requirements.
• Collaborate with HW architects to define critical features and verification teams to ensure feature correctness.
• Coordinate with timing, VLSI, and Physical design teams to meet timing, interface, and routability requirements.
• Work with FPGA and S/W teams to prototype designs and facilitate software testing.
• Execute post-silicon verification and debug.

Required Skills

• 4+ years of design experience.
• Proven RTL design experience of complex design units across at least two or three projects.
• Expertise in Verilog.
• Deep understanding of ASIC design flow, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, and bring-up.
• Experience with design and verification tools such as VCS, Debussy, or GDB.
• Bachelor's degree or MS in a related field.

Preferred Skills

• Design experience in memory subsystem or network interconnect IP.
• Scripting knowledge in Python, Perl, or shell.
• Experience leading small teams of 2-3 members.

Key Skills

Education

Bachelor's degree