Description

You will own DFT architecture and implementation tasks within a semiconductor design environment.

Responsibilities

• Implement DFT architecture using Scan, ATPG, Simulation, and GLS methodologies.
• Execute MBIST insertion and simulation processes to ensure design integrity.
• Write and maintain technical documentation, including uArchitecture and SoC Integration Specifications.
• Debug simulation issues and develop automation scripts to streamline design workflows.

Required Skills

• 4+ years of experience in DFT engineering.
• Hands-on experience with Scan, ATPG, Simulation, and GLS.
• Proficiency with Synopsys, Cadence, or Mentor tools including Tetramax, Modus, and Tessent.
• Practical knowledge of MBIST insertion and simulation.
• Strong simulation debugging skills.
• Scripting proficiency in Perl, Python, Shell, or TCL.
• B.Tech or M.Tech degree.

Key Skills

Education

B.Tech/M.Tech