Description

You will own the micro-architecture and RTL development of design modules.

This role is on-site.

Responsibilities

• Micro-architect features to meet performance, power, and area requirements.
• Collaborate with hardware architects and verification teams to define critical features and ensure correctness.
• Coordinate with timing, VLSI, and physical design teams to satisfy timing, interface, and routability constraints.
• Work with FPGA and software teams to prototype designs and facilitate testing.
• Execute post-silicon verification and debug.

Required Skills

• 4+ years of design experience with proven RTL design of complex units across at least two or three projects.
• Expertise in Verilog and deep understanding of the ASIC design flow.
• Knowledge of RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, and bring-up.
• Experience with design and verification tools such as VCS, Debussy, or GDB.
• Bachelor's degree or MS in a related field.

Preferred Skills

• Design experience in memory subsystem or network interconnect IP.
• Scripting knowledge in Python, Perl, or shell.
• Experience leading small teams of 2-3 members.

Key Skills

Education

Bachelor's degree