Description

You will create full-custom layouts for analog and mixed-signal IP blocks, ensuring physical verification and optimization for area and performance.

This role is on-site.

Responsibilities

• Create layout designs for analog and mixed-signal circuits in coordination with functional leads.
• Convert circuit schematics into efficient physical layouts.
• Optimize layouts for area, performance, and quality.
• Perform physical verification to ensure DRC, LVS, and ERC clean layouts.
• Support multiple sections of modules and sub-blocks as required.

Required Skills

• 5+ years of experience in analog layout design.
• Bachelor's degree in a relevant field.
• Strong understanding of CMOS technology fundamentals, including NMOS/PMOS devices and layout layers.
• Proficiency in analog layout techniques such as matching (common centroid, interdigitated) and symmetry/shielding.
• Hands-on experience with Cadence Virtuoso or similar EDA layout tools.
• Ability to read and interpret circuit schematics.
• Experience with physical verification processes including DRC, LVS, and parasitic extraction.

Preferred Skills

• Hands-on experience with standard cell layouts.
• Familiarity with Calibre or Assura.

Key Skills

Education

Bachelor's degree