Description

You will own backend implementation tasks including synthesis, timing closure, and power analysis for gate-level netlists.

This role is on-site.

Responsibilities

• Run logic and physical synthesis to generate optimized gate-level netlists for timing, area, and power.
• Debug timing, area, and congestion issues in collaboration with RTL and physical designers.
• Perform power estimation at RTL and gate levels to identify reduction opportunities.
• Develop timing constraints for RTL synthesis and PrimeTime-STA for blocks and SOC top-levels.

Required Skills

• 10+ years of experience in backend implementation, synthesis, timing closure, and power analysis.
• Expertise with PTPX for power analysis.
• Experience with RTL synthesis and design optimization for Power, Performance, and Area (PPA).
• Proficiency in Python and TCL for building EDA tool flows.
• Experience with CDC and RDC.
• Ability to perform RTL Lint and manage waiver creation.
• Experience analyzing inter-block timing and establishing IO budgets for partition blocks.

Preferred Skills

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.

Key Skills

Education

ANY GRADUATE