Description

You will own the design and verification flow for ASIC development, integrating cell libraries and functional units into SoC full chip designs.

Responsibilities

• Perform RTL design, simulation, and logic design for SoC integration.
• Execute the SoC design flow from high-level synthesis through place and route, timing, and power analysis.
• Develop test and execution plans by collaborating with micro-architects, firmware engineers, and SoC designers.
• Implement verification methodologies including UVM, formal property verification, and embedded C-based FW co-simulation.
• Analyze equipment to establish operation infrastructure and conduct experimental testing.

Required Skills

• 5+ years of experience in hardware or chip design environments.
• Proficiency in SystemVerilog or VHDL.
• Strong experience with Python, Make, and object-oriented programming.
• Hands-on experience with Linux and Git.
• Solid understanding of fundamental digital logic design.
• Experience with SoC and ASIC design processes.
• Proven debugging and problem-solving capabilities.

Preferred Skills

• Deep understanding of ASIC design and verification methodologies.
• Experience with Open Source tools and CI/CD pipelines.

Key Skills

Education

ANY GRADUATE