Description

You will lead Design for Debug and Design for Test activities for complex SoCs across frontend and backend domains.

This role is remote.

Responsibilities

• Lead frontend DfD/T activities using hands-on RTL coding and architecture expertise.
• Design and implement DfD/T structures for Program Reset Control, Memory BIST, and Clock Control blocks.
• Drive DfD/T planning and execution to ensure high testability and debug capabilities.
• Execute memory repair functionality checks and define test strategies.
• Develop RTL solutions for Analog IP testability in sub-10nm technology nodes.

Required Skills

• 10+ years of experience in Design for Debug (DfD) and Design for Test (DfT).
• Expertise in RTL coding and frontend DfD/T architecture.
• Backend DfD/T experience including scan insertion and manufacturing-related DfD/T.
• Hands-on experience with complex SoC design at sub-10nm technology nodes.
• Proficiency in Analog IP testability.
• Technical knowledge of Memory BIST and clock control structures.
• Proven ability to lead teams and drive end-to-end DfD/T implementation.
• Valid work visa or first-priority citizenship in specified regions for export security clearance.

Preferred Skills

• 15+ years of experience in DfD/DfT roles.

Key Skills

Education

Any Graduate