Description

You will own the design-for-test strategy, implementation, and validation for complex SoCs and high-speed processor cores.

This role is on-site.

Responsibilities

• Implement scan insertion, ATPG, MBIST, JTAG, IO BIST, and scan compression.
• Execute at-speed testing and manage silicon bring-up activities.
• Debug and validate DFT features on ATE platforms.
• Collaborate with cross-functional teams to resolve defect types and fault models.
• Apply DFT, DFD, and DFM techniques to ensure testability and yield.

Required Skills

• 7+ years of experience with DFT/DFD/DFM for high-speed processor cores and complex SoCs.
• Proficiency with Tessent or Test Kompress tools.
• Hands-on experience with ATPG, MBIST, JTAG, and IO BIST.
• Experience using industry-standard simulation, ATPG, and MBIST tools.
• Knowledge of defect types, fault models, and silicon bring-up.
• Experience with debug and validation of DFT features on ATE.
• Strong analytical and communication skills.

Preferred Skills

• Experience with scripting languages.

Key Skills

Education

Any Graduate