Description

You will develop and maintain scalable verification environments for IP, subsystem, or SoC levels.

Responsibilities

• Construct highly scalable, configurable, and reusable DV and performance verification environments.
• Write SystemVerilog and SystemC models for simulation.
• Develop UVM models, checkers, and stimulus, including UVM register models using constrained random methodology.
• Compose test plans and validation vectors to ensure functional completeness.
• Implement design for verification strategies including assertion-based design, code coverage, functional coverage, and gate-level simulation.

Required Skills

• 5+ years of experience in ASIC design or verification.
• Proficiency in SystemVerilog (SV).
• Hands-on experience with UVM.
• Experience with C++.
• Knowledge of AXI and AMBA protocols.
• Experience with industry standard verification tools.
• Strong problem-solving and communication skills.

Key Skills

Education

Any Graduate