Description

You will execute the complete verification cycle for IP, sub-systems, and SoC levels.

Responsibilities

• Define and implement IP/SoC verification plans and build test benches to enable verification.
• Develop functional tests based on the verification test plan.
• Drive verification to closure using functional and code coverage metrics.
• Debug, root cause, and resolve functional failures in partnership with the Design team.
• Collaborate with Design, Model, Emulation, and Silicon validation teams to ensure design quality.

Required Skills

• B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science.
• 5+ years of experience in hardware verification.
• Hands-on experience with Verilog, System Verilog, and C/C++ based verification.
• Proficiency with UVM or OVM methodologies for IP/sub-system and SoC level verification.
• Experience architecting and implementing Design Verification infrastructure.
• Experience with EDA tools and scripting in Python, Perl, or Shell to build verification flows.

Preferred Skills

• Experience developing UVM-based verification environments from scratch.
• Verification experience with Data-center applications such as Video, AI/ML, or Networking designs.
• Experience with revision control systems like Mercurial (Hg), Git, or SVN.

Key Skills

Education

B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science