Description

You will own the complete verification cycle for IP, sub-systems, and SoC levels.

This role is on-site.

Responsibilities

• Define and implement verification plans and build test benches for IP and SoC.
• Develop functional tests based on verification plans and drive verification to closure using coverage metrics.
• Debug, root cause, and resolve functional failures in partnership with the Design team.
• Collaborate with Design, Model, Emulation, and Silicon validation teams to ensure design quality.
• Architect and implement Design Verification infrastructure.

Required Skills

• B.S or M.S degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of experience in hardware verification.
• Hands-on experience with Verilog, SystemVerilog, and C/C++ based verification.
• Proficiency with UVM or OVM methodologies for IP/sub-system and SoC level verification.
• Experience with EDA tools and scripting in Python, Perl, or Shell to build verification flows.

Preferred Skills

• Experience developing UVM-based verification environments from scratch.
• Verification experience with Data-center applications such as Video, AI/ML, or Networking designs.

Key Skills

Education

B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science