Description

You will own the end-to-end verification process for IP, sub-systems, and SoC levels.

This role is on-site.

Responsibilities

• Define and implement IP/SoC verification plans and build test benches.
• Develop functional tests based on the verification test plan.
• Drive verification to closure using functional and code coverage metrics.
• Debug, root-cause, and resolve functional failures in partnership with Design teams.
• Collaborate with Model, Emulation, and Silicon validation teams to ensure design quality.

Required Skills

• 7+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification.
• Experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM.
• Ability to architect and implement Design Verification infrastructure.
• Proficiency in EDA tools and scripting with Python, TCL, Perl, or Shell.
• Strong background in executing the full verification cycle.
• Proficiency in Git, SVN, or Mercurial for revision control.
• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.

Preferred Skills

• Experience developing UVM-based verification environments from scratch.
• Experience verifying GPU/CPU designs or ARM/RISC-V based sub-systems.
• Verification of high-speed interfaces such as PCIe, RoCE, DDR, HBM, or Ethernet.

Key Skills

Education

Any Graduate