Description

You will own the verification environment for new silicon projects and manage all aspects of verification methodology.

Responsibilities

• Implement test benches using UVM and SystemVerilog to run regressions at both RTL and gate levels.
• Develop test and coverage plans, review specifications, and define methodologies to ensure design requirements are met.
• Debug failures in real time, specifically addressing high throughput, low latency pipelines, and dynamic power management.
• Manage verification regression suites at the RTL and netlist levels to test corner case conditions.
• Generate and report DV metrics, including bug tracking and code coverage, while providing feedback to the design team.

Required Skills

• 5+ years of industry experience bringing silicon ICs into high-volume production.
• Extensive experience with UVM and full chip verification.
• Strong proficiency in Verilog and simulation tools.
• Demonstrated ability in debugging and troubleshooting in real time.
• Expertise in writing scripts using Perl, Python, Tcl, awk, or sed to automate verification tasks.
• Experience with low-level programming in C/C++.
• Functional understanding of constrained random verification, functional coverage, and code coverage.
• Knowledge of ARMv8, interconnect, memory coherence, and memory architectures.

Preferred Skills

• Experience with Secure boot and Secure JTAG.

Key Skills

Education

Any Graduate