Description

Key Skills: SystemVerilog, UVM, Test Bench Development, Python, Perl, TCL, Verilog RTL, EDA Tools, I2C, SPI

Good to Have Skills: Experience with Ethernet protocols (RGMII, RMII interface), advanced troubleshooting techniques for verification issues, code coverage analysis, black box testing methodologies, mixed-signal product verification experience, electronic design automation tools and simulators.

Roles & Responsibilities:

• Develop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM methodologies.
• Create and maintain verification plans, focusing on functional and code coverage metrics to ensure design quality.
• Perform black box testing for complex designs to identify potential issues early in the verification cycle.
• Debug verification issues using advanced troubleshooting techniques and provide effective solutions to complex problems.
• Collaborate with design teams to align verification strategies with project requirements and meet quality standards.
• Create and maintain detailed documentation for verification processes and results for future reference.
• Participate in design reviews and provide verification insights to improve overall product quality and reliability.
• Apply scripting skills to automate verification tasks and improve efficiency of the verification workflow.

Experience Required: 2-4 years of relevant experience in digital design verification

Education: Bachelor's or Master's degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, or related field

Key Skills

Education

Any Graduate