Description

You will own the verification strategy and execution for mixed-signal and digital designs, ensuring functional and code coverage metrics are met.

Responsibilities

• Develop and execute comprehensive test benches using SystemVerilog and UVM methodologies.
• Perform black box testing on complex designs to identify issues early in the verification cycle.
• Debug verification issues using advanced troubleshooting techniques and provide effective solutions.
• Create and maintain verification plans, focusing on functional and code coverage metrics.
• Collaborate with design teams to align verification strategies with project requirements.

Required Skills

• 2-4 years of relevant experience in digital design verification.
• Proficiency in SystemVerilog, UVM, and Test Bench Development.
• Strong scripting skills in Python, Perl, and TCL.
• Experience with Verilog RTL and EDA Tools.
• Knowledge of I2C and SPI protocols.

Preferred Skills

• Experience with Ethernet protocols (RGMII, RMII interface).
• Mixed-signal product verification experience.
• Code coverage analysis and black box testing methodologies.

Key Skills

Education

Any Graduate