Description

Own the functional verification of complex ASIC and SoC designs, ensuring correctness through rigorous testing and debug.

This role is on-site.

Responsibilities

• Develop and execute comprehensive verification plans for digital designs.
• Create testbenches and test cases using UVM and SystemVerilog to achieve functional and code coverage targets.
• Debug design failures and collaborate with RTL designers to resolve bugs.
• Verify IP and SoC-level designs for protocols including AXI, APB, PCIe, and DDR.
• Develop automation scripts in Python, Perl, or TCL to improve verification efficiency.

Required Skills

• 12+ years of experience in ASIC/SoC design verification.
• Deep expertise in UVM methodology and SystemVerilog.
• Proficiency with industry-standard simulation and debug tools such as VCS, Questa, and Verdi.
• Strong scripting skills in Python, Perl, and TCL.
• Experience with constrained random and directed testing methodologies.
• Understanding of common digital protocols (AXI, APB, PCIe, DDR).

Preferred Skills

• Experience with advanced debug techniques and coverage closure strategies.

Key Skills

Education

Any Gradute