Description

You will own the verification environment for new silicon projects, ensuring ASIC design validation from RTL through silicon bring-up.

This role is on-site.

Responsibilities

• Implement test benches in UVM and SystemVerilog, running RTL and gate-level regressions.
• Debug high-throughput, low-latency pipeline designs and dynamic power management issues.
• Setup verification regression suites at RTL and netlist levels to test corner case conditions.
• Collaborate with design teams to review specifications, define methodologies, and close design holes.
• Generate and report DV metrics, including bug tracking, code coverage, and functional coverage.

Required Skills

• 5+ years of industry experience in ASIC verification and silicon bring-up.
• Strong expertise in UVM and SystemVerilog.
• Proficiency in Verilog, Perl, Python, awk, and Tcl for automation and scripting.
• Experience with simulation tools, Formality, and equivalence checking.
• Knowledge of ARMv8 architecture, memory coherence, and interconnects.
• Familiarity with industry standard interfaces (USB, PCIe, MIPI, SDIO, DDR).
• Understanding of low-power verification (UPF) and C/C++ low-level programming.
• BS or MS in Computer Science or Electrical Engineering.

Key Skills

Education

Any Graduate