Description

You will own the verification strategy for complex interconnectivity components across SoC, chiplet, or multi-chiplet systems.

Responsibilities

• Create test plans for highly configurable IPs connecting components across SoC, chiplet, or multi-chiplet systems.
• Write UVM/SystemVerilog code to implement test plans, checkers, and scoreboard functionality.
• Collaborate with software teams to define and implement configurable test benches.
• Partner with design teams on test planning, failure debugging, and coverage analysis.

Required Skills

• 6+ years of experience in ASIC Verification.
• Strong experience in Frontend Verification.
• Proficiency in Verification methodologies and debugging.
• Hands-on expertise in ASIC Verification.
• Experience with Universal Verification Methodology (UVM).
• Working knowledge of System Verilog.

Preferred Skills

• Familiarity with VHDL.

Key Skills

Education

Any Graduate