Description

Own the verification process to ensure product reliability and performance.

Responsibilities

• Develop and execute test cases within SV/UVM environments.
• Debug failing test cases to isolate design and verification environment issues.
• Architect, build, and maintain the verification stack.
• Collaborate with the team to achieve functional coverage closure.
• Develop regressable tests to ensure product stability and compliance with Ethernet standards from 100G to 800G.

Required Skills

• 5+ years of experience in design verification.
• Proficiency in SystemVerilog (SV) and UVM.
• Expertise in Ethernet standards, specifically 100G to 800G.
• Proven ability to architect and maintain a verification stack.
• Experience developing regressable tests.
• Strong debugging and functional verification skills.
• Ability to drive coverage closure.

Education

• Any Graduate degree.

Key Skills

Education

Any Graduate