Description

You will own verification activities for highly configurable IPs across SoC, chiplet, or multi-chiplet systems.

This role is on-site.

Responsibilities

• Create test plans for interconnectivity IPs.
• Write UVM/SystemVerilog code to implement test plans, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable test benches.
• Partner with design teams on test plans, failure debug, and coverage closure.

Required Skills

• 6+ years of professional experience in ASIC Verification.
• Strong hands-on expertise in Frontend Verification.
• Proficiency in Universal Verification Methodology (UVM).
• Working knowledge of SystemVerilog.
• Familiarity with VHDL.
• Experience with verification methodologies and debugging.

Key Skills

Education

Any Graduate