Description

You will own the verification process for IP and SoC level designs to ensure functional correctness.

This role is on-site.

Responsibilities

• Define verification scope and develop comprehensive test plans and infrastructure.
• Implement and analyze SystemVerilog assertions and coverage metrics, including code, toggle, and functional coverage.
• Develop, execute, and analyze verification test cases to resolve design issues.
• Collaborate with architects, designers, and pre/post-silicon verification teams.

Required Skills

• 4+ years of experience in Design Verification (DV), GLS, or PAGLS.
• Strong proficiency in SystemVerilog and UVM.
• Experience with processor-based SoC level verification in mixed environments (Native, Verilog, SystemVerilog, UVM).
• Hands-on experience with VCS, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs).
• Proficiency in C/C++ and SystemVerilog verification languages.
• Working knowledge of AXI-AMBA protocol variants.
• Ability to use scripting languages including Shell, Makefile, and Perl.
• Solid understanding of ASIC flow and design concepts.

Preferred Skills

• Prior work experience specifically at the IP or SoC level.

Key Skills

Education

Any Graduate