Description

You will lead the verification of DDR memory controller and PHY designs to ensure compliance with DDR3, DDR4, and DDR5 standards.

Responsibilities

• Develop scalable and reusable verification environments and testbenches using SystemVerilog and UVM.
• Create detailed verification plans covering corner cases, timing, and protocol validation.
• Run simulations and debug design issues using Questa, VCS, or ModelSim through waveform analysis and assertion-based verification.
• Manage regression testing to ensure continuous validation and early detection of design issues.
• Implement formal verification techniques to validate timing, data flow, and critical DDR operations.

Required Skills

• 4+ years of experience in DDR verification.
• Expertise in SystemVerilog and UVM (Universal Verification Methodology).
• Hands-on experience with DDR3, DDR4, and DDR5 memory interface protocols.
• Proficiency in simulation and debugging tools such as Questa, VCS, or ModelSim.
• Ability to execute verification plan creation and protocol compliance testing.
• Experience with regression testing and managing verification coverage.
• Knowledge of formal verification techniques.
• Competency in waveform analysis and assertion-based verification.
• Ability to validate command, data, and clock synchronization, burst transfers, and power management.

Key Skills

Education

Any Graduate