Description

Own the verification of Digital ASIC designs using UVM and SystemVerilog methodologies.

Responsibilities

• Develop UVM/SystemVerilog components including sequences, drivers, monitors, scoreboards, and agents.
• Implement SystemVerilog Assertions (SVA) to validate design functionality.
• Write and maintain verification environments using OVM/UVM methodologies.
• Utilize scripting languages to automate verification tasks and workflows.

Required Skills

• 3+ years of experience in Design Verification.
• Proficiency in SystemVerilog and UVM/OVM methodologies.
• Experience developing verification components: sequences, drivers, monitors, scoreboards, and agents.
• Hands-on experience with SystemVerilog Assertions (SVA).
• Solid understanding of Digital ASIC Design.
• Proficiency in Python, Perl, and Shell scripting.
• Bachelor's degree or equivalent graduate level education.
• Ability to work within the PST timezone.

Key Skills

Education

Any Graduate