Description

Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes.

Exposure to RTL design, software development, formal verification, or other related domains.

Good understanding of computer organization/architecture.

Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics

Requirements added by the job poster

• 5+ years of work experience with Functional Verification

• 5+ years of work experience with Web Development

• 5+ years of work experience with Design

Key Skills

Education

Any Graduate