Description

You will focus on SOC verification using C-based testing and SystemVerilog environments.

Responsibilities

• Develop and execute processor-based C tests for SOC verification, including test coding, compilation, and loading into testbenches.
• Debug simulation failures using a methodical approach and standard EDA tools.
• Perform connectivity verification using JasperGold to resolve debug issues quickly.
• Manage test development and simulation workflows across the verification lifecycle.

Required Skills

• 7+ years of experience in design verification.
• Strong proficiency in SystemVerilog and UVM.
• Extensive experience with C-based testing for SOC verification and failure debugging.
• Deep understanding of ARM processor-based SOCs and AXI/AHB protocols.
• Hands-on experience with popular EDA tools for simulation and test development.
• Proven ability to debug complex hardware issues logically.
• Degree in any graduate field.

Preferred Skills

• Experience with CoreSight debug or JasperGold connectivity verification.
• Knowledge of dynamic CDC verification, clock sweep tests, or complex reset architectures.
• Experience debugging issues within a GLS environment.

Key Skills

Education

Any Graduate