Description

Drive functional verification for next-generation IP and subsystems within the Control Fabric.

This role is on-site.

Responsibilities

• Develop and maintain functional verification tests using UVM at the subsystem level.
• Build testbench components to support next-generation IP development.
• Maintain and improve existing test libraries for IP-level testing.
• Lead technical verification for IPs within the Control Fabric.
• Provide technical support to cross-functional teams.

Required Skills

• SystemVerilog (SV) expertise.
• UVM verification methodology experience.
• Proficiency in C and C++.
• Experience with AXI protocol.
• Experience with Bootcode Verification.
• Scripting knowledge in Perl, Ruby, or Makefile.
• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Key Skills

Education

Any graduate