Description

You ensure the functional correctness, performance, and adherence to specifications for complex digital ASIC Core/IP designs, focusing on deep, unit, and core-level verification.

Responsibilities

• Develop comprehensive Core Verification Plans based on the unit's micro-architecture and design specification.
• Architect and implement reusable verification environments using System Verilog/UVM.
• Create and execute constrained-random and directed tests to achieve high functional and code coverage.
• Analyze simulation results, debug complex failures, and collaborate with the design team to root-cause issues.
• Develop and maintain scripts (Python/Perl) to enhance the verification flow and regression management.

Required Skills

• Mandatory expertise in SystemVerilog and UVM.
• 7+ years of hands-on verification expertise.
• Strong grasp of digital logic design and verification methodologies.
• Experience verifying digital systems using standard IP components (e.g., microprocessor cores, memory subsystems).
• Familiarity with AMBA bus protocols and SoC system debug infrastructure.
• Experience with micro-architecture, Verilog/SystemVerilog, Synthesis, Lint, and CDC checks.
• Proficiency with industry-standard EDA simulation and debug tools.
• Experience with scripting languages like Python and Perl.
• Solid abilities in debugging and root-cause analysis.

Key Skills

Education

Any Graduate