Description

You ensure functional correctness, performance, and specification adherence for complex digital ASIC Core/IP designs through deep, unit, and core-level verification.

This role is on-site.

Responsibilities

• Develop comprehensive Core Verification Plans based on unit micro-architecture and design specifications.
• Architect and implement reusable verification environments using SystemVerilog and UVM.
• Create and execute constrained-random and directed tests to achieve high functional and code coverage.
• Analyze simulation results, debug complex failures, and collaborate with the design team to root-cause issues.
• Develop and maintain Python/Perl scripts to enhance the verification flow and regression management.

Required Skills

• 7+ years of hands-on verification expertise.
• Expertise in SystemVerilog and UVM.
• Strong grasp of digital logic design and verification methodologies.
• Experience verifying digital systems using standard IP components (e.g., microprocessor cores, memory subsystems).
• Familiarity with AMBA bus protocols and SoC system debug infrastructure.
• Experience with micro-architecture, Verilog/SystemVerilog, Synthesis, Lint, and CDC checks.
• Proficiency with industry-standard EDA simulation and debug tools.
• Proficiency in scripting languages like Python and Perl.
• Solid abilities in debugging and root-cause analysis.

Preferred Skills

• Experience with Python and Perl for flow automation.

Key Skills

Education

Any Graduate