Description

Own ASIC IP verification strategies and execute test plans to ensure design quality.

This role is on-site.

Responsibilities

• Develop IP verification strategies and test plans in collaboration with architects and design leads.
• Build verification environments using UVM and SystemVerilog.
• Write tests and regressions to identify bugs and resolve architecture or design issues.
• Develop functional coverage models, assertion checkers, and scoreboards.
• Perform RTL, assertion, and functional coverage analysis, including gate-level simulations.

Required Skills

• 8+ years of experience in ASIC design, verification, or related fields.
• Strong expertise in UVM and SystemVerilog.
• Extensive experience with scripting tools and programming languages, specifically PERL and Python.
• Hands-on experience with ASIC IP Verification and UVM development.
• Proficiency with bus protocols, specifically AHB and AXI.
• Ability to interpret specifications and standards to develop thorough test plans.
• Experience navigating test benches, analyzing coverage, and performing debug.

Preferred Skills

• Bachelor's degree in Science, Engineering, or a related field.

Key Skills

Education

Any Graduate