Description

You will own the verification methodology and ensure uniform standards across ASIC designs.

This role is on-site.

Responsibilities

• Implement test benches using UVM and SystemVerilog for RTL and gate-level regressions.
• Develop test and coverage plans by reviewing specifications and chip architecture.
• Debug design failures including high throughput, low latency pipelines, and dynamic power management.
• Generate and report DV metrics for bug tracking and code coverage.
• Set up verification regression suites at RTL and netlist levels to test corner cases.

Required Skills

• 5+ years of industry experience bringing silicon ICs into high-volume production.
• Extensive experience with UVM and full chip verification.
• Strong proficiency in Verilog and simulation tools.
• Deep knowledge of ARMv8, interconnects, memory coherence, and memory architectures.
• Expertise in writing Perl, Python, awk, sed, and Tcl scripts to automate verification tasks for CPU and peripherals (USB, PCIe, MIPI, SDIO, DDR).
• Advanced knowledge of ASIC design flows: RTL design, equivalence checking, timing analysis, scan insertion, and test pattern generation.
• Experience with low-level system programming in C/C++.
• Functional understanding of constrained random verification, functional coverage, and code coverage.
• Experience with low power verification using UPF.

Preferred Skills

• Knowledge of low-power camera and imaging systems.
• Experience with formal verification tools.
• Familiarity with CPU Security, Secure boot, and Secure JTAG.

Key Skills

Education

Any Graduate