Description

You will own verification closure for ASIC designs, focusing on scale test benches, AXI, NOC/Crossbar, and performance regression. You will drive coverage closure and triage in a fast-moving, documentation-light environment.

Responsibilities

• Develop and maintain scale test benches using SystemVerilog and UVM for AXI, NOC, and Crossbar protocols.
• Execute performance regression and triage to identify and resolve verification gaps.
• Drive coverage closure through rigorous simulation and analysis.
• Automate verification flows and scripts using Python and Perl.
• Report progress and technical status to customers on a daily or weekly basis.

Required Skills

• 8+ years of experience in ASIC design verification.
• Strong expertise in SystemVerilog and UVM.
• Hands-on experience with AXI, NOC, and Crossbar architectures.
• Proficiency in Python and Perl for automation and scripting.
• Experience with verification closure and performance regression.
• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• Ability to work independently with minimal documentation.

Preferred Skills

• Experience with Amazon tools, flows, and methodologies.

Key Skills

Education

Master's degree