Description

You will own the verification process for complex IPs and support chip-level verification infrastructure.

This role is on-site.

Responsibilities

• Create verification plans (VR) based on chip requirements.
• Develop UVM/OVM testbenches and simulation models.
• Execute IP verification across RTL, Power Aware, and Gate Level domains.
• Collaborate with functional leads to meet technical milestones.
• Communicate technical issues to non-specialist audiences.

Required Skills

• 4+ years of experience in digital IP verification.
• Strong proficiency in Verilog and SystemVerilog.
• Hands-on experience with UVM or OVM methodologies.
• Deep understanding of ASIC/SoC design and verification flows.
• Experience with Design Verification Testing (DVT).
• Ability to handle complex IP verification requirements.
• Strong logical thinking and technical expression.

Preferred Skills

• Experience with SV assertion, coverage, or formal verification.
• Knowledge of AMBA (AXI/AHB/APB), PCIe, or X86/ARM/8051 architectures.
• Scripting proficiency in Python or Perl.

Key Skills

Education

Any Graduate