Description

You will own the functional verification of complex SoC and ASIC/FPGA designs.

Responsibilities

• Develop and execute verification plans using SystemVerilog and UVM to validate complex designs.
• Design and implement testbenches and verification environments to ensure functional accuracy.
• Debug and troubleshoot complex hardware issues through detailed analysis.
• Document verification processes, methodologies, and results for reproducibility.

Required Skills

• 4 to 12 years of experience in design verification processes and methodologies.
• Proficiency in SystemVerilog (SV) and UVM.
• Experience with VHDL.
• Hands-on experience with formal verification methodologies.
• Working knowledge of Ethernet and PCIe protocols.
• Experience verifying RISC-V processors and low power designs.
• Experience using Synopsys VCS, Verdi, or Formality.
• Experience with Mentor Graphics Questa or similar simulation tools.
• Any Graduate degree.

Key Skills

Education

Any Graduate