Description

Own the verification of graphics IPs and SoCs across prototype and SoC design environments. Drive DV plan execution through post-silicon bringup and validation.

Responsibilities

• Develop and implement test plans, methodologies, and tool flows for graphics IPs.
• Define IP/SoC verification plans, testbenches, and simulation/emulation coverage.
• Build and leverage automated DV environments spanning prototypes, SoCs, and hardware emulation platforms.
• Support the integration of IP block tests into larger SoC environment tests.

Required Skills

• 6+ years of experience in RTL verification for FPGAs or ASICs.
• SystemVerilog UVM testbenches, coverage analysis, and SVA.
• FPGA and SoC design flows, tools, and methodology.
• Industry standard RTL simulators, emulators, and waveform debugging tools.
• Python3 scripting.
• BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.

Preferred Skills

• Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with PCIe, USB, MIPI, or on-chip bus protocols like AXI, AXI-Lite, and AHB.
• Software/Hardware Co-simulation (DPI/VPI).

Key Skills

Education

Master's degree